A computer system may include multiple processors where each processor includes a component, commonly referred to as a memory controller, configured to control the issuance of read or write commands by the processor to a system memory. A read command may refer to a request to read data at a particular address location in system memory. A write command may refer to a request to write data, provided by the processor, to a particular address location in system memory.
Each processor may be coupled to the system memory through a series of memory buffers chained to one another. These memory buffers are required as the data rate at which the commands (read and write commands) and data are transmitted by the processor is greater than the rate at which the system memory is accessed. Each memory buffer may be associated with particular banks of memory in the system memory. Each memory buffer is configured to store the read and write commands, along with any data, received from a processor that are directed to its associated banks of memory in the system memory.
The interconnections between a processor and the first memory buffer in the series of chained memory buffers as well as between the memory buffers themselves are referred to herein as “signal lines”. Data, such as read and write commands described above, may be transmitted from the processor to the appropriate memory buffer (including being transmitted amongst the chained memory buffers to reach the appropriate memory buffer) through these signal lines. These interconnections may also include what is referred to herein as a “spare line” or a “spare signal line”. The spare line may be used to replace a signal line that has become defective thereby ensuring the correct transfer of data.
When a signal line is detected as being defective, the defective signal line is replaced with the spare line by deactivating, i.e., turning off, the computer system. Once the computer system is deactivated, the defective signal line is replaced with the spare signal line. However, by requiring to deactivate the computer system, a significant amount of time (time that the computer system is deactivated plus the time to replace the defective signal line with the spare signal line plus the time to reactivate the computer system) elapses before data can be resent from the processor to the memory buffers. If the computer system did not have to be deactivated in order to switch the defective signal line with the spare signal line, then the time that the processor could not send information to the memory buffers would be greatly reduced.
Therefore, there is a need in the art to switch a defective signal line with a spare signal line without shutting down the computer system.